TY - JOUR
T1 - A 1.8-65 fJ/conv.-step 64 dB SNDR Continuous - Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
AU - Timmermans, Martijn
AU - van Oosterhout, Kyle
AU - Fattori, Marco
AU - Harpe, Pieter J.A.
AU - Liu, Yao-Hong
AU - Cantatore, Eugenio
PY - 2024/4
Y1 - 2024/4
N2 - This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm2. In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoMW as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.
AB - This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm2. In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoMW as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.
KW - Continuous-time (CT)
KW - dynamic biased comparator
KW - event-driven
KW - level crossing (LC) analog-to-digital converter (ADC)
UR - http://www.scopus.com/inward/record.url?scp=85187244666&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2024.3352735
DO - 10.1109/JSSC.2024.3352735
M3 - Article
SN - 0018-9200
VL - 59
SP - 1194
EP - 1203
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 4
M1 - 10433522
ER -