This paper presents a low-power fast-startup wideband VGA with a 6th-order low-pass filter function for UWB radios. A DC-coupled 6-stage open-loop topology is proposed, which includes DC offset calibration and fast-startup biasing circuits. The prototype in 90nm CMOS occupies only 0.075mm2, including decoupling capacitors and digital interfacing. The circuit consumes 1.6mW from a 1V supply, achieves -1.2dB up to 37.7dB gain with a programmable bandwidth from 80MHz to 460MHz, and achieves a startup-time of 12ns.
|Title of host publication||Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2011|