A 16 bit 16-core Flexible 40 nm DAC Platform

This chapter presents a flexible DAC design in 40 nm CMOS technology. It features large scale functional unary segmentation. 16 parallel sub-DACs construct a flexible DAC platform. The pre-processor is realized in the form of a functional “binary-to-unary” decoder, which generates the sub-DAC input words w_i(nT ), i = 1, 2, 3, … 16. For the sake of simplified testing, the sub-DACs are internally grouped in packs to form one 15 bit sub-DAC (8 12 bit sub-DACs are connected at their outputs), one 14 bit sub-DAC (4 12 bit sub-DACs), one 13 bit (2 12 bit sub-DACs), and two 12 bit sub-DACs. Each sub-DAC features algorithmic segmentation of 8 LSB binary bits and 4 MSB unary bits (15 unary currents). The transistor design features thin and thick oxide circuits. All digital circuits are implemented with thin oxide transistors to save area and to increase speed. The DAC current cells are implemented with thick oxide transistors to interface the DAC to 2.5 V. The occupied silicon area of the flexible DAC platform is the smallest reported in the literature. It is 0.05 mm² per 12 bit sub-DAC unit, i.e. 0.8 mm² for the whole flexible 16 bit DAC platform.