A 14mW 500MSPS 59dB SFDR open-loop track-and-hold circuit

This paper presents the design and implementation of an open-loop Track-and-Hold circuit in a CMOS 0:18¹m technology. Also, experimental measurement results are discussed. The open-loop architecture is motivated by the fact that it can potentially reduce the power consumption, increase the speed of operation and improve the portability to new process generations. The limited linearity, related to open-loop structures, is improved by applying a combination of three linearization techniques: source degeneration and cross-coupling of the output buffer and clock-boosting of the sampling switches. The simulation and measurement results reveal that the presented T&H achieves a high sampling speed of 500MSPS while consuming 14mW at a 1.8V power supply. Because of the linearization techniques, an SFDR of 59dB is obtained. Moreover, the simplicity of the open-loop structure allows simple migration to future process generations. Benchmarking reveals that the proposed open-loop architecture provides a suitable solution for state-of-the-art AD converters.