A 14bit 200 MS/s DAC with SFDR>78 dBc, IM3

Y. Tang, J. Briaire, K. Doris, R.H.M. Veldhoven, van, P.C.W. Beek, van, J.A. Hegt, A.H.M. Roermund, van

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This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 µm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3
Original languageEnglish
Pages (from-to)1371-1381
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number6
Publication statusPublished - 2011


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