A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

Hongfei Hu; Qian Qi; Jian Xiao; Yufeng Guo; Hao Gao; Yi Zhang

doi:10.1109/ICMMT52847.2021.9618087

A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

Hongfei Hu, Qian Qi, Jian Xiao, Yufeng Guo, Hao Gao, Yi Zhang

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

Original language	English
Title of host publication	2021 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021 - Proceedings
Subtitle of host publication	Proceedings
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	3
ISBN (Electronic)	978-1-6654-3437-9
DOIs	https://doi.org/10.1109/ICMMT52847.2021.9618087
Publication status	Published - 1 Dec 2021
Event	International Conference on Microwave and Millimeter Wave Technology (ICMMT2021) - Nanjing, China Duration: 23 May 2021 → 26 May 2021 http://www.em-conf.com/icmmt2021/

Conference

Conference	International Conference on Microwave and Millimeter Wave Technology (ICMMT2021)
Country/Territory	China
City	Nanjing
Period	23/05/21 → 26/05/21
Internet address	http://www.em-conf.com/icmmt2021/

Bibliographical note

POSTER Session: MP4P

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10.1109/ICMMT52847.2021.9618087

Cite this

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title = "A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology",

abstract = "This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.",

author = "Hongfei Hu and Qian Qi and Jian Xiao and Yufeng Guo and Hao Gao and Yi Zhang",

note = "POSTER Session: MP4P; International Conference on Microwave and Millimeter Wave Technology (ICMMT2021) ; Conference date: 23-05-2021 Through 26-05-2021",

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doi = "10.1109/ICMMT52847.2021.9618087",

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Hu, H, Qi, Q, Xiao, J, Guo, Y, Gao, H & Zhang, Y 2021, A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology. in 2021 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021 - Proceedings: Proceedings., 9618087, Institute of Electrical and Electronics Engineers, International Conference on Microwave and Millimeter Wave Technology (ICMMT2021), Nanjing, China, 23/05/21. https://doi.org/10.1109/ICMMT52847.2021.9618087

A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology. / Hu, Hongfei; Qi, Qian; Xiao, Jian; Guo, Yufeng; Gao, Hao; Zhang, Yi.

2021 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021 - Proceedings: Proceedings. Institute of Electrical and Electronics Engineers, 2021. 9618087.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

AU - Hu, Hongfei

AU - Qi, Qian

AU - Xiao, Jian

AU - Guo, Yufeng

AU - Gao, Hao

AU - Zhang, Yi

N1 - POSTER Session: MP4P

PY - 2021/12/1

Y1 - 2021/12/1

N2 - This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

AB - This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

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U2 - 10.1109/ICMMT52847.2021.9618087

DO - 10.1109/ICMMT52847.2021.9618087

M3 - Conference contribution

BT - 2021 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers

T2 - International Conference on Microwave and Millimeter Wave Technology (ICMMT2021)

Y2 - 23 May 2021 through 26 May 2021

ER -

A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

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