A 14b 200MS/s DAC with SFDR>78dBc, IM3

Yongjian Tang, J. Briaire, K. Doris, R.H.M. Veldhoven, van, P.C.W. Beek, van, J.A. Hegt, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14µm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3
Original languageDutch
Title of host publicationProceeding of 2010 IEEE Symposium on VLSI Circuits, 16-18 June 2010, Honolulu, USA
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4244-5454-9
DOIs
Publication statusPublished - 2010

Cite this

Tang, Y., Briaire, J., Doris, K., Veldhoven, van, R. H. M., Beek, van, P. C. W., Hegt, J. A., & Roermund, van, A. H. M. (2010). A 14b 200MS/s DAC with SFDR>78dBc, IM3. In Proceeding of 2010 IEEE Symposium on VLSI Circuits, 16-18 June 2010, Honolulu, USA Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSIC.2010.5560316