Abstract
This paper describes a 14-GHz 8-bit direct digital synthesizer(DDS)which is implemented using a 0.7-μm InP double hetero-junction bipolar transistor (DHBT) process. The DDS presented uses a sin-weighted nonlinear DAC to achieve a phase-to-amplitude ROM-less architecture which can make the best of speed advantage of the InP DHBT process for medium to large scale mixed signal integrated circuits. A simplified pipelined phase accumulator is used to reduce power consumption. The average value of SFDR of the output signal of the DDS in the Nyquist bandwidth is -24.8 dBc. The circuit integrates 2122 transistors, consumes a power of 2.4-W, and has a Figure of Merit (FOM) of 5.83GHz/W.
Original language | English |
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Title of host publication | 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 3 |
ISBN (Electronic) | 978-1-7281-2496-4 |
DOIs | |
Publication status | Published - Aug 2019 |
Event | 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) - Nanjing, China Duration: 28 Aug 2019 → 30 Aug 2019 |
Conference
Conference | 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) |
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Country/Territory | China |
City | Nanjing |
Period | 28/08/19 → 30/08/19 |