A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

Yuting Shen; Hanyue Li; Harijot Singh Bindra; Eugenio Cantatore; Pieter Harpe

doi:10.1109/TCSII.2023.3259821

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

Yuting Shen (Corresponding author)
, Hanyue Li
, Harijot Singh Bindra
, Eugenio Cantatore
, Pieter Harpe

Research output: Contribution to journal › Article › Academic › peer-review

11 Citations (Scopus)

1231 Downloads (Pure)

Abstract

DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes 0.656μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

Original language	English
Article number	10077761
Pages (from-to)	1719-1723
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	70
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2023.3259821
Publication status	Published - 1 May 2023

Bibliographical note

Funding Information:
This work was supported by the Dutch Research Council (NWO) under Grant 16594.

Funding

This work was supported by the Dutch Research Council (NWO) under Grant 16594.

Keywords

Analog-to-digital converter (ADC)
flying capacitor sampling
input range compensation
mismatch error shaping (MES)
successive approximation register (SAR)

Access to Document

10.1109/TCSII.2023.3259821

202305 TCASII paperFinal author version , 756 KBLicence: Unspecified
pdfFinal published version, 2.06 MBLicence: TAVERNE

Cite this

@article{c3c73eb3653b4d788aff751a3da4294b,

title = "A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation",

abstract = "DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes 0.656μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.",

keywords = "Analog-to-digital converter (ADC), flying capacitor sampling, input range compensation, mismatch error shaping (MES), successive approximation register (SAR)",

author = "Yuting Shen and Hanyue Li and Bindra, \{Harijot Singh\} and Eugenio Cantatore and Pieter Harpe",

note = "Funding Information: This work was supported by the Dutch Research Council (NWO) under Grant 16594. ",

year = "2023",

month = may,

day = "1",

doi = "10.1109/TCSII.2023.3259821",

language = "English",

volume = "70",

pages = "1719--1723",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers",

number = "5",

}

TY - JOUR

T1 - A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

AU - Shen, Yuting

AU - Li, Hanyue

AU - Bindra, Harijot Singh

AU - Cantatore, Eugenio

AU - Harpe, Pieter

N1 - Funding Information: This work was supported by the Dutch Research Council (NWO) under Grant 16594.

PY - 2023/5/1

Y1 - 2023/5/1

N2 - DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes 0.656μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

AB - DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes 0.656μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

KW - Analog-to-digital converter (ADC)

KW - flying capacitor sampling

KW - input range compensation

KW - mismatch error shaping (MES)

KW - successive approximation register (SAR)

UR - https://www.scopus.com/pages/publications/85151510457

U2 - 10.1109/TCSII.2023.3259821

DO - 10.1109/TCSII.2023.3259821

M3 - Article

AN - SCOPUS:85151510457

SN - 1549-7747

VL - 70

SP - 1719

EP - 1723

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 5

M1 - 10077761

ER -

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

Abstract

Bibliographical note

Funding

Keywords

Access to Document

Other files and links

Fingerprint

Cite this