Abstract
We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a Gm-C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm2.
| Original language | English |
|---|---|
| Article number | 7453191 |
| Pages (from-to) | 116-120 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 64 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 1 Feb 2017 |
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Keywords
- Analog-to-digital converter (ADC)
- complementary metal-oxide semiconductor (CMOS)
- redundancy
- successive approximation register (SAR)
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A 14-bit 30-MS/s 38-mW SAR ADC using noise filter gear shifting. / Kramer, Martin; Janssen, Erwin; Doris, Kostas; Murmann, Boris.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 2, 7453191, 01.02.2017, p. 116-120.Research output: Contribution to journal › Article › Academic › peer-review
TY - JOUR
T1 - A 14-bit 30-MS/s 38-mW SAR ADC using noise filter gear shifting
AU - Kramer, Martin
AU - Janssen, Erwin
AU - Doris, Kostas
AU - Murmann, Boris
PY - 2017/2/1
Y1 - 2017/2/1
N2 - We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a Gm-C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm2.
AB - We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a Gm-C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm2.
KW - Analog-to-digital converter (ADC)
KW - complementary metal-oxide semiconductor (CMOS)
KW - redundancy
KW - successive approximation register (SAR)
UR - http://www.scopus.com/inward/record.url?scp=85011690574&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2554858
DO - 10.1109/TCSII.2016.2554858
M3 - Article
AN - SCOPUS:85011690574
VL - 64
SP - 116
EP - 120
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 2
M1 - 7453191
ER -