Abstract
We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a Gm-C preamplifier. This approach allows us to relax precision and enhance speed during noncritical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm2.
Original language | English |
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Article number | 7453191 |
Pages (from-to) | 116-120 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 64 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1 Feb 2017 |
Keywords
- Analog-to-digital converter (ADC)
- complementary metal-oxide semiconductor (CMOS)
- redundancy
- successive approximation register (SAR)