A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers

Yanxiang Huang, A. Kapoor, R. Rutten, J. Pineda de Gyvez

Research output: Contribution to journalArticleAcademicpeer-review

3 Citations (Scopus)
1 Downloads (Pure)

Abstract

In this paper we analyze the architecture of a 13 bits 4.096. GHz multi-stage decimation filter for multi-standard radio receivers. It also explores the benefits of Carry-Save format numbers in this decimation filter. After trading off between area and power consumption, we propose to use shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. The proposed decimation filter chain exploits the advantage of all architectures and exhibit the best area-power trade-off. It is implemented using 45 nm CMOS technology. The proposed design reduces power by 13.7% without area overhead, compared with a conventional filter chain using only binary number.

Original languageEnglish
Pages (from-to)869–878
JournalMicroprocessors and Microsystems
Volume39
Issue number8
DOIs
Publication statusPublished - Nov 2015

Keywords

  • Carry-Save number
  • Computer arithmetic
  • Decimation filter
  • Signal processing

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