A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers

Y. Huang; A. Kapoor; R. Rutten; J. Pineda de Gyvez

doi:10.1109/NORCHIP.2013.6702042

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers

Y. Huang, A. Kapoor, R. Rutten, J. Pineda de Gyvez

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

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Abstract

In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area.

Original language	English
Title of host publication	NORCHIP 2013 Conference, 11-13 November 2013, Vilnius, Lithuana
Place of Publication	Brussels
Publisher	IEEE Computer Society
ISBN (Print)	9781479916474
DOIs	https://doi.org/10.1109/NORCHIP.2013.6702042
Publication status	Published - 2013
Event	NORCHIP 2013 - Vilnius, Lithuania Duration: 11 Nov 2013 → 12 Nov 2013

Conference

Conference	NORCHIP 2013
Country	Lithuania
City	Vilnius
Period	11/11/13 → 12/11/13

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10.1109/NORCHIP.2013.6702042

Cite this

@inproceedings{92425e2863e0445981783f6f5212fd34,

title = "A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers",

abstract = "In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area.",

author = "Y. Huang and A. Kapoor and R. Rutten and {Pineda de Gyvez}, J.",

year = "2013",

doi = "10.1109/NORCHIP.2013.6702042",

language = "English",

isbn = "9781479916474",

booktitle = "NORCHIP 2013 Conference, 11-13 November 2013, Vilnius, Lithuana",

publisher = "IEEE Computer Society",

address = "United States",

note = "NORCHIP 2013 ; Conference date: 11-11-2013 Through 12-11-2013",

}

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers. / Huang, Y.; Kapoor, A.; Rutten, R.; Pineda de Gyvez, J.

NORCHIP 2013 Conference, 11-13 November 2013, Vilnius, Lithuana. Brussels : IEEE Computer Society, 2013. 6702042.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers

AU - Huang, Y.

AU - Kapoor, A.

AU - Rutten, R.

AU - Pineda de Gyvez, J.

PY - 2013

Y1 - 2013

N2 - In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area.

AB - In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area.

UR - http://www.scopus.com/inward/record.url?scp=84893567458&partnerID=8YFLogxK

U2 - 10.1109/NORCHIP.2013.6702042

DO - 10.1109/NORCHIP.2013.6702042

M3 - Conference contribution

AN - SCOPUS:84893567458

SN - 9781479916474

BT - NORCHIP 2013 Conference, 11-13 November 2013, Vilnius, Lithuana

PB - IEEE Computer Society

CY - Brussels

T2 - NORCHIP 2013

Y2 - 11 November 2013 through 12 November 2013

ER -

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers

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