A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

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Abstract

This paper reports design, optimization, efficiency and measurement results of the 12 bits dual-residue multi-step A/D converter. The calibration procedure based on the steepest-descent estimation method is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. The prototype A/D converter with performance of 68.6 dB SNDR, 70.3 dB SNR, 78.1 dB SFDR, 11.1 ENOB at 60 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 55 mW and measures 0.75 mm2. The on-chip calibration logic occupies an area of 0.14 mm2 and consumes 11 mW of power.
Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, ISLPED 2011, 1-3 August 2011, Fukuoka, Japan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages187-192
ISBN (Print)978-1-61284-658-3
DOIs
Publication statusPublished - 2011
Eventconference; ISLPED 2011; 2011-08-01; 2011-08-03 -
Duration: 1 Aug 20113 Aug 2011

Conference

Conferenceconference; ISLPED 2011; 2011-08-01; 2011-08-03
Period1/08/113/08/11
OtherISLPED 2011

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