A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C

Fabio Sebastiano; Lucien J. Breems; Kofi A.A. Makinwa; Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta

doi:10.1109/ISSCC.2010.5433895

A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C

Fabio Sebastiano, Lucien J. Breems, Kofi A.A. Makinwa, Salvatore Drago, Domine M.W. Leenaerts, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

43 Citations (Scopus)

Abstract

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm², which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

Original language	English
Title of host publication	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	312-313
Number of pages	2
ISBN (Electronic)	978-1-4244-6036-6
ISBN (Print)	978-1-4244-6033-5
DOIs	https://doi.org/10.1109/ISSCC.2010.5433895
Publication status	Published - 18 May 2010
Event	57th IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, United States Duration: 7 Feb 2010 → 11 Feb 2010 Conference number: 57

Conference

Conference	57th IEEE International Solid-State Circuits Conference, ISSCC 2010
Abbreviated title	ISSCC 2010
Country/Territory	United States
City	San Francisco
Period	7/02/10 → 11/02/10

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10.1109/ISSCC.2010.5433895

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Sebastiano, F., Breems, L. J., Makinwa, K. A. A., Drago, S., Leenaerts, D. M. W., & Nauta, B. (2010). A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 312-313). Article 5433895 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2010.5433895

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title = "A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C",

abstract = "This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.",

author = "Fabio Sebastiano and Breems, {Lucien J.} and Makinwa, {Kofi A.A.} and Salvatore Drago and Leenaerts, {Domine M.W.} and Bram Nauta",

year = "2010",

month = may,

day = "18",

doi = "10.1109/ISSCC.2010.5433895",

language = "English",

isbn = "978-1-4244-6033-5",

pages = "312--313",

booktitle = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "57th IEEE International Solid-State Circuits Conference, ISSCC 2010, ISSCC 2010 ; Conference date: 07-02-2010 Through 11-02-2010",

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Sebastiano, F, Breems, LJ, Makinwa, KAA, Drago, S, Leenaerts, DMW & Nauta, B 2010, A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers., 5433895, Institute of Electrical and Electronics Engineers, Piscataway, pp. 312-313, 57th IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, California, United States, 7/02/10. https://doi.org/10.1109/ISSCC.2010.5433895

A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. / Sebastiano, Fabio; Breems, Lucien J.; Makinwa, Kofi A.A. et al.
2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers, 2010. p. 312-313 5433895.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Sebastiano, Fabio

AU - Breems, Lucien J.

AU - Makinwa, Kofi A.A.

AU - Drago, Salvatore

AU - Leenaerts, Domine M.W.

AU - Nauta, Bram

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N2 - This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

AB - This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim.

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M3 - Conference contribution

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BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 57th IEEE International Solid-State Circuits Conference, ISSCC 2010

Y2 - 7 February 2010 through 11 February 2010

ER -

Sebastiano F, Breems LJ, Makinwa KAA, Drago S, Leenaerts DMW, Nauta B. A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers. 2010. p. 312-313. 5433895 doi: 10.1109/ISSCC.2010.5433895

A 1.2V 10μW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C

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