This paper presents an 8-bit asynchronous SAR ADC for flexible, low energy radios. The prototype in a 90nm CMOS technology achieves an ENOB of 7.7bit at a sampling frequency of 10.24MS/s while consuming 26.3µW from a 1V supply. Excellent power efficiency is achieved by using asynchronous dynamic logic, custom 0.5fF unit capacitors, a low-complexity design and an optimized layout. The measured prototype achieves a FoM of 12fJ/conversion-step, which is a 2.5x improvement over previous state-of-the-art 8-bit converters. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6nW.
|Title of host publication||Proceedings of the 36th European Solid-State Circuits Conference (ESSCIRC 2010), 14-16 September 2010, Seville, Spain|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2010|
Harpe, P. J. A., Zhou, C., Wang, X., Dolmans, G., & Groot, de, H. W. H. (2010). A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios. In Proceedings of the 36th European Solid-State Circuits Conference (ESSCIRC 2010), 14-16 September 2010, Seville, Spain (pp. 214-217). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2010.5619891