A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS

C.H. Lin, F. Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, K. Bult

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.
Original languageEnglish
Title of host publicationISSCC 2009
Pages74-75a
DOIs
Publication statusPublished - 2009
Event56th IEEE International Solid-State Circuits Conference (ISSCC 2009) - San Francisco, CA , United States
Duration: 8 Feb 2009 → 12 Feb 2009
Conference number: 56

Conference

Conference56th IEEE International Solid-State Circuits Conference (ISSCC 2009)
Abbreviated titleISSCC 2009
CountryUnited States
CitySan Francisco, CA
Period8/02/09 → 12/02/09
Other"Adaptive Circuits and Systems"

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Lin, C. H., Goes, F., Westra, J., Mulder, J., Lin, Y., Arslan, E., ... Bult, K. (2009). A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS. In ISSCC 2009 (pp. 74-75a) https://doi.org/10.1109/ISSCC.2009.4977314