Abstract
A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.
Original language | English |
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Title of host publication | ISSCC 2009 |
Pages | 74-75a |
DOIs | |
Publication status | Published - 2009 |
Event | 56th IEEE International Solid-State Circuits Conference (ISSCC 2009) - San Francisco, CA , United States Duration: 8 Feb 2009 → 12 Feb 2009 Conference number: 56 |
Conference
Conference | 56th IEEE International Solid-State Circuits Conference (ISSCC 2009) |
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Abbreviated title | ISSCC 2009 |
Country | United States |
City | San Francisco, CA |
Period | 8/02/09 → 12/02/09 |
Other | "Adaptive Circuits and Systems" |