A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS

C.H. Lin; F. Goes; J. Westra; J. Mulder; Y. Lin; E. Arslan; E. Ayranci; X. Liu; K. Bult

doi:10.1109/ISSCC.2009.4977314

A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS

C.H. Lin, F. Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, K. Bult

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.

Original language	English
Title of host publication	ISSCC 2009
Pages	74-75a
DOIs	https://doi.org/10.1109/ISSCC.2009.4977314
Publication status	Published - 2009
Event	56th IEEE International Solid-State Circuits Conference (ISSCC 2009) - San Francisco, CA , United States Duration: 8 Feb 2009 → 12 Feb 2009 Conference number: 56

Conference

Conference	56th IEEE International Solid-State Circuits Conference (ISSCC 2009)
Abbreviated title	ISSCC 2009
Country	United States
City	San Francisco, CA
Period	8/02/09 → 12/02/09
Other	"Adaptive Circuits and Systems"

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10.1109/ISSCC.2009.4977314

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@inproceedings{3704d30557ca44db9c6bead3d907fb02,

title = "A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS",

abstract = "A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.",

author = "C.H. Lin and F. Goes and J. Westra and J. Mulder and Y. Lin and E. Arslan and E. Ayranci and X. Liu and K. Bult",

year = "2009",

doi = "10.1109/ISSCC.2009.4977314",

language = "English",

isbn = "978-1-4244-3458-9",

pages = "74--75a",

booktitle = "ISSCC 2009",

note = "56th IEEE International Solid-State Circuits Conference (ISSCC 2009), ISSCC 2009 ; Conference date: 08-02-2009 Through 12-02-2009",

}

TY - GEN

T1 - A 12b 2.9GS/s DAC with IM3>60dB beyond 1 GHz in 65nm CMOS

AU - Lin, C.H.

AU - Goes, F.

AU - Westra, J.

AU - Mulder, J.

AU - Lin, Y.

AU - Arslan, E.

AU - Ayranci, E.

AU - Liu, X.

AU - Bult, K.

N1 - Conference code: 56

PY - 2009

Y1 - 2009

N2 - A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.

AB - A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 «-60dBc beyond 1GHz while driving a 50¿ load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz.

U2 - 10.1109/ISSCC.2009.4977314

DO - 10.1109/ISSCC.2009.4977314

M3 - Conference contribution

SN - 978-1-4244-3458-9

SP - 74-75a

BT - ISSCC 2009

T2 - 56th IEEE International Solid-State Circuits Conference (ISSCC 2009)

Y2 - 8 February 2009 through 12 February 2009

ER -