A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS

C.H. Lin, F.M.L. Goes, van der, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, Xiadong Liu, K. Bult

Research output: Contribution to journalArticleAcademicpeer-review

112 Citations (Scopus)
1160 Downloads (Pure)

Abstract

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <¿-60 dBc beyond 1 GHz while driving a 50 ¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with ¿always-ON¿ biasing.
Original languageEnglish
Pages (from-to)3285-3293
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number12
DOIs
Publication statusPublished - 2009

Fingerprint

Dive into the research topics of 'A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS'. Together they form a unique fingerprint.

Cite this