A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS

C.H. Lin; F.M.L. Goes, van der; J. Westra; J. Mulder; Y. Lin; E. Arslan; E. Ayranci; Xiadong Liu; K. Bult

doi:10.1109/JSSC.2009.2032624

A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS

C.H. Lin, F.M.L. Goes, van der, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, Xiadong Liu, K. Bult

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Abstract

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <Â¿-60 dBc beyond 1 GHz while driving a 50 Â¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with Â¿always-ONÂ¿ biasing.

Original language	English
Pages (from-to)	3285-3293
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2009.2032624
Publication status	Published - 2009

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title = "A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS",

abstract = "A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <{\^A}¿-60 dBc beyond 1 GHz while driving a 50 {\^A}¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with {\^A}¿always-ON{\^A}¿ biasing.",

author = "C.H. Lin and {Goes, van der}, F.M.L. and J. Westra and J. Mulder and Y. Lin and E. Arslan and E. Ayranci and Xiadong Liu and K. Bult",

year = "2009",

doi = "10.1109/JSSC.2009.2032624",

language = "English",

volume = "44",

pages = "3285--3293",

journal = "IEEE Journal of Solid-State Circuits",

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publisher = "Institute of Electrical and Electronics Engineers",

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T1 - A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS

AU - Lin, C.H.

AU - Goes, van der, F.M.L.

AU - Westra, J.

AU - Mulder, J.

AU - Lin, Y.

AU - Arslan, E.

AU - Ayranci, E.

AU - Liu, Xiadong

AU - Bult, K.

PY - 2009

Y1 - 2009

N2 - A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <Â¿-60 dBc beyond 1 GHz while driving a 50 Â¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with Â¿always-ONÂ¿ biasing.

AB - A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <Â¿-60 dBc beyond 1 GHz while driving a 50 Â¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with Â¿always-ONÂ¿ biasing.

U2 - 10.1109/JSSC.2009.2032624

DO - 10.1109/JSSC.2009.2032624

M3 - Article

SN - 0018-9200

VL - 44

SP - 3285

EP - 3293

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 12

ER -

A 12 bit 2.9 GS/s DAC with IM3 <-60 dBc beyond 1 GHz in 65 nm CMOS

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