A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

M. Liu; A.H.M. van Roermund; P.J.A. Harpe

doi:10.1109/ESSCIRC.2017.8094568

A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

M. Liu, A.H.M. van Roermund, P.J.A. Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

4 Downloads (Pure)

Abstract

Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

Original language	English
Title of host publication	43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	231-234
Number of pages	4
ISBN (Electronic)	978-1-5090-5025-3
ISBN (Print)	978-1-5090-5026-0
DOIs	https://doi.org/10.1109/ESSCIRC.2017.8094568
Publication status	Published - 2 Nov 2017
Event	43rd European Solid State Circuits Conference (ESSCIRC 2017) - Leuven, Belgium Duration: 11 Sept 2017 → 14 Sept 2017 Conference number: 43 http://www.esscirc-essderc2017.org/

Conference

Conference	43rd European Solid State Circuits Conference (ESSCIRC 2017)
Abbreviated title	ESSCIRC 2017
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17
Other	47th European Solid-State Device Research Conference (ESSDERC 2017) & 43rd European Solid-State Circuits Conference (ESSCIRC 2017), 11-14 September 2017, Leuven, Belgium
Internet address	http://www.esscirc-essderc2017.org/

Keywords

Area efficient
Charge-redistribution
Low power
Reference-voltage driving
SAR ADC

Access to Document

10.1109/ESSCIRC.2017.8094568

Cite this

Liu, M., van Roermund, A. H. M., & Harpe, P. J. A. (2017). A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. In 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium (pp. 231-234). [8094568] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2017.8094568

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title = "A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference",

abstract = "Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.",

keywords = "Area efficient, Charge-redistribution, Low power, Reference-voltage driving, SAR ADC",

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Liu, M, van Roermund, AHM & Harpe, PJA 2017, A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. in 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium ., 8094568, Institute of Electrical and Electronics Engineers, Piscataway, pp. 231-234, 43rd European Solid State Circuits Conference (ESSCIRC 2017), Leuven, Belgium, 11/09/17. https://doi.org/10.1109/ESSCIRC.2017.8094568

A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. / Liu, M.; van Roermund, A.H.M.; Harpe, P.J.A.

43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium . Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 231-234 8094568.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

AU - Liu, M.

AU - van Roermund, A.H.M.

AU - Harpe, P.J.A.

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PY - 2017/11/2

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N2 - Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

AB - Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

KW - Area efficient

KW - Charge-redistribution

KW - Low power

KW - Reference-voltage driving

KW - SAR ADC

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DO - 10.1109/ESSCIRC.2017.8094568

M3 - Conference contribution

SN - 978-1-5090-5026-0

SP - 231

EP - 234

BT - 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 43rd European Solid State Circuits Conference (ESSCIRC 2017)

Y2 - 11 September 2017 through 14 September 2017

ER -

A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

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Keywords

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