A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.
LanguageEnglish
Title of host publication43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages231-234
ISBN (Electronic)978-1-5090-5025-3
ISBN (Print)978-1-5090-5026-0
DOIs
StatePublished - 2017
Event47th European Solid-State Device Research Conference (ESSDERC 2017) & 43rd European Solid-State Circuits Conference (ESSCIRC 2017), 11-14 September 2017, Leuven, Belgium - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017
http://www.esscirc-essderc2017.org/

Conference

Conference47th European Solid-State Device Research Conference (ESSDERC 2017) & 43rd European Solid-State Circuits Conference (ESSCIRC 2017), 11-14 September 2017, Leuven, Belgium
Abbreviated titleESSDERC/ESSCIRC
CountryBelgium
CityLeuven
Period11/09/1714/09/17
Internet address

Fingerprint

Electric potential
Capacitors
Compensation and Redress
Voltage drop

Cite this

Liu, M., van Roermund, A. H. M., & Harpe, P. J. A. (2017). A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. In 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium (pp. 231-234). Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ESSCIRC.2017.8094568
Liu, M. ; van Roermund, A.H.M. ; Harpe, P.J.A./ A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium . Piscataway : Institute of Electrical and Electronics Engineers, 2017. pp. 231-234
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title = "A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference",
abstract = "Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.",
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Liu, M, van Roermund, AHM & Harpe, PJA 2017, A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. in 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium . Institute of Electrical and Electronics Engineers, Piscataway, pp. 231-234, 47th European Solid-State Device Research Conference (ESSDERC 2017) & 43rd European Solid-State Circuits Conference (ESSCIRC 2017), 11-14 September 2017, Leuven, Belgium, Leuven, Belgium, 11/09/17. DOI: 10.1109/ESSCIRC.2017.8094568

A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. / Liu, M.; van Roermund, A.H.M.; Harpe, P.J.A.

43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium . Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 231-234.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - Liu,M.

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PY - 2017

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N2 - Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

AB - Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.

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M3 - Conference contribution

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BT - 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium

PB - Institute of Electrical and Electronics Engineers

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Liu M, van Roermund AHM, Harpe PJA. A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. In 43rd IEEE European Solid State Circuits Conference , ESSCIRC 2017, 11-14 September 2017, Leuven, Belgium . Piscataway: Institute of Electrical and Electronics Engineers. 2017. p. 231-234. Available from, DOI: 10.1109/ESSCIRC.2017.8094568