Abstract
This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.
| Original language | English |
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| Title of host publication | ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-4 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781665488235 |
| DOIs | |
| Publication status | Published - 2022 |
| Event | 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022 - Glasgow, United Kingdom Duration: 24 Oct 2022 → 26 Oct 2022 |
Conference
| Conference | 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022 |
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| Country/Territory | United Kingdom |
| City | Glasgow |
| Period | 24/10/22 → 26/10/22 |
Bibliographical note
Funding Information:This work with project number 16594 is financed by the Dutch Research Council (NWO).
Funding
This work with project number 16594 is financed by the Dutch Research Council (NWO).
Keywords
- duty cycle
- input driver
- low power
- SAR ADC
- unity-gain buffer