A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter

Hanyue Li; Yuting Shen; Eugenio Cantatore; Pieter Harpe

doi:10.1109/NEWCAS57931.2023.10198037

A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter

Hanyue Li
, Yuting Shen
, Eugenio Cantatore
, Pieter Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.

Original language	English
Title of host publication	2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)
Publisher	Institute of Electrical and Electronics Engineers
Pages	1-5
Number of pages	5
ISBN (Electronic)	979-8-3503-0024-6
DOIs	https://doi.org/10.1109/NEWCAS57931.2023.10198037
Publication status	Published - 7 Aug 2023
Event	21st IEEE Interregional NEWCAS Conference, NEWCAS 2023 - Edinburgh, United Kingdom Duration: 26 Jun 2023 → 28 Jun 2023

Conference

Conference	21st IEEE Interregional NEWCAS Conference, NEWCAS 2023
Country/Territory	United Kingdom
City	Edinburgh
Period	26/06/23 → 28/06/23

Funding

This work with project number 16594 is financed by the Dutch Research Council (NWO).

Funders
Nederlandse Organisatie voor Wetenschappelijk Onderzoek

Keywords

duty cycle
low power
multiple feedback filter
SAR ADC

Access to Document

10.1109/NEWCAS57931.2023.10198037

202306 NEWCAS paperFinal author version , 1.04 MBLicence: Unspecified

Cite this

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title = "A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter",

abstract = "This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36\% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.",

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author = "Hanyue Li and Yuting Shen and Eugenio Cantatore and Pieter Harpe",

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booktitle = "2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "21st IEEE Interregional NEWCAS Conference, NEWCAS 2023 ; Conference date: 26-06-2023 Through 28-06-2023",

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Li, H, Shen, Y, Cantatore, E & Harpe, P 2023, A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter. in 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)., 10198037, Institute of Electrical and Electronics Engineers, pp. 1-5, 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, 26/06/23. https://doi.org/10.1109/NEWCAS57931.2023.10198037

A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter. / Li, Hanyue; Shen, Yuting; Cantatore, Eugenio et al.
2023 21st IEEE Interregional NEWCAS Conference (NEWCAS). Institute of Electrical and Electronics Engineers, 2023. p. 1-5 10198037.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Cantatore, Eugenio

AU - Harpe, Pieter

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N2 - This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.

AB - This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.

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KW - low power

KW - multiple feedback filter

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U2 - 10.1109/NEWCAS57931.2023.10198037

DO - 10.1109/NEWCAS57931.2023.10198037

M3 - Conference contribution

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BT - 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

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ER -

A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter

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Keywords

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