A 10-b 20-MS/s SAR ADC with DAC-Compensated Discrete-Time Reference Driver

Research output: Contribution to journalArticleAcademicpeer-review

Abstract

Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm² where 8.6% is occupied by the reference driver.

LanguageEnglish
Pages417-427
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number2
DOIs
StatePublished - 1 Feb 2019

Fingerprint

Digital to analog conversion
Capacitors
Redundancy
Capacitance

Keywords

  • Area efficient
  • Calibration
  • Capacitance
  • Capacitors
  • charge-redistribution (CR)
  • discrete time
  • low power
  • Power demand
  • reference driver
  • Registers
  • SAR analog-to-digital converter.
  • Switches
  • Switching circuits

Cite this

@article{2276600b95f94ca786fe0ab1819dac65,
title = "A 10-b 20-MS/s SAR ADC with DAC-Compensated Discrete-Time Reference Driver",
abstract = "Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm² where 8.6{\%} is occupied by the reference driver.",
keywords = "Area efficient, Calibration, Capacitance, Capacitors, charge-redistribution (CR), discrete time, low power, Power demand, reference driver, Registers, SAR analog-to-digital converter., Switches, Switching circuits",
author = "Maoqiang Liu and {van Roermund}, {Arthur H.M.} and Pieter Harpe",
year = "2019",
month = "2",
day = "1",
doi = "10.1109/JSSC.2018.2873711",
language = "English",
volume = "54",
pages = "417--427",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers",
number = "2",

}

A 10-b 20-MS/s SAR ADC with DAC-Compensated Discrete-Time Reference Driver. / Liu, Maoqiang (Corresponding author); van Roermund, Arthur H.M.; Harpe, Pieter.

In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 2, 01.02.2019, p. 417-427.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - A 10-b 20-MS/s SAR ADC with DAC-Compensated Discrete-Time Reference Driver

AU - Liu,Maoqiang

AU - van Roermund,Arthur H.M.

AU - Harpe,Pieter

PY - 2019/2/1

Y1 - 2019/2/1

N2 - Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm² where 8.6% is occupied by the reference driver.

AB - Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm² where 8.6% is occupied by the reference driver.

KW - Area efficient

KW - Calibration

KW - Capacitance

KW - Capacitors

KW - charge-redistribution (CR)

KW - discrete time

KW - low power

KW - Power demand

KW - reference driver

KW - Registers

KW - SAR analog-to-digital converter.

KW - Switches

KW - Switching circuits

UR - http://www.scopus.com/inward/record.url?scp=85055170706&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2018.2873711

DO - 10.1109/JSSC.2018.2873711

M3 - Article

VL - 54

SP - 417

EP - 427

JO - IEEE Journal of Solid-State Circuits

T2 - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -