A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT

This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.