A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT

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Abstract

This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)978-1-4673-6853-7
DOIs
Publication statusPublished - 25 Sep 2017
Event50th IEEE International Symposium on Circuits and Systems (ISCAS 2017) - Baltimore, United States
Duration: 28 May 201731 May 2017

Conference

Conference50th IEEE International Symposium on Circuits and Systems (ISCAS 2017)
Abbreviated titleISCAS 2017
CountryUnited States
CityBaltimore
Period28/05/1731/05/17

Fingerprint

Resistors
Electric potential
Temperature
Electric power utilization
Internet of things
Threshold voltage
Transistors
Capacitors

Keywords

  • CMOS
  • duty-cycling
  • IoT
  • low power
  • low VDD
  • resistor-less
  • small chip area
  • voltage reference

Cite this

Liu, M., van Roermund, A., & Harpe, P. (2017). A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050287] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2017.8050287
Liu, M. ; van Roermund, A. ; Harpe, P. / A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2017.
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abstract = "This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34{\%} active time. At 5 corners, the reference voltage Huctuates with 3{\%} at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.",
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Liu, M, van Roermund, A & Harpe, P 2017, A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050287, Institute of Electrical and Electronics Engineers, Piscataway, 50th IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, United States, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050287

A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT. / Liu, M.; van Roermund, A.; Harpe, P.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2017. 8050287.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.

AB - This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3∼31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.

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Liu M, van Roermund A, Harpe P. A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2017. 8050287 https://doi.org/10.1109/ISCAS.2017.8050287