A 0.8V 0.8mm 2 bluetooth 5/BLE digital-intensive transceiver with a 2.3mW phase-tracking RX utilizing a hybrid loop filter for interference resilience in 40nm CMOS

Ming Ding, Xiaoyan Wang, Peng Zhang, Yuming He, Stefano Traferro, Kenichi Shibata, Minyoung Song, Hannu Korpela, Keisuke Ueda, Yao Hong Liu, Christian Bachmann, Kathleen Philips

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

18 Citations (Scopus)

Abstract

This paper presents a low-voltage (0.8V) ultra-low-power Bluetooth 5(BT5)/Bluetooth Low Energy(BLE) digitally-intensive transceiver for IoT applications. In comparison to BLE, BT5 has a 2x higher data-rate and 4x longer range, while having >8x longer packet. The BLE prior arts [1-5] have made significant efforts to minimize the power consumption for longer battery life, as well as the chip area. However, the prior-art Cartesian BLE radios consume namely 6 to 10mW [1-3] to achieve a <-94dBm sensitivity but with a relatively high supply voltage (V DD ) (>1.0V). Operating a BLE RF transceiver at a lower V DD (e.g., <0.85V) not only extends the battery life by up to 50% [3], and reduces the Power-Management-Unit complexity, but also can accommodate a wider range of energy sources (e.g., harvesters). A recent single-channel phase-tracking RX [5] demonstrated a potential to reduce the chip area and the power consumption at a V DD down to 0.85V. However, it suffers from a degraded sensitivity due to a poor deviation frequency control and an excessive loop delay, limited ACR (Adjacent-Channel-Rejection) due to the digitally-controlled-oscillator (DCO) side-lobe energy, and an undefined initial carrier frequency due to the lack of a PLL/FLL that could have a risk of tracking to an interference. This work presents a fully-integrated 0.8V phase-domain BT5/BLE-combo transceiver, including a PHY-layer digital baseband (DBB), and addresses the above-mentioned issues by employing two key techniques: 1) a hybrid loop filter with a loop-delay compensation for DCO side-lobe suppression to enhance interference tolerance, and 2) an all-digital PLL(ADPLL)-based digital FM interface shared between RX and TX is employed, including a deviation frequency calibration, and it also precisely defines the initial frequency. Moreover, the PHY-layer DBB that supports a packet-mode phase-tracking RX operation is also demonstrated.

Original languageEnglish
Title of host publication2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages446-448
Number of pages3
ISBN (Electronic)978-1-5090-4940-0
DOIs
Publication statusPublished - 8 Mar 2018
Event65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
Duration: 11 Feb 201815 Feb 2018

Conference

Conference65th IEEE International Solid-State Circuits Conference, ISSCC 2018
CountryUnited States
CitySan Francisco
Period11/02/1815/02/18

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