Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 µm × 200 µm. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.
Harpe, P. J. A., Zhou, C., Philips, K. J. P., & Groot, de, H. W. H. (2011). A 0.8mW 5bit 250MS/s time-interleaved asynchronous digital slope ADC. IEEE Journal of Solid-State Circuits, 46(11), 2450-2457. https://doi.org/10.1109/JSSC.2011.2164031