Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a non-oversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using calibration techniques. A 2-channel time-interleaved 5 bit asynchronous digital slope ADC was implemented in a 90 nm CMOS technology. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1 V supply.
|Title of host publication||Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2010|
Harpe, P. J. A., Zhou, C., Philips, K. J. P., & Groot, de, H. W. H. (2010). A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. In Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASSCC.2010.5716582