A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC

P.J.A. Harpe, C. Zhou, K.J.P. Philips, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a non-oversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using calibration techniques. A 2-channel time-interleaved 5 bit asynchronous digital slope ADC was implemented in a 90 nm CMOS technology. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1 V supply.
Original languageEnglish
Title of host publicationProceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
ISBN (Print)978-1-4244-8300-6
DOIs
Publication statusPublished - 2010

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Clocks
Calibration
Sampling

Cite this

Harpe, P. J. A., Zhou, C., Philips, K. J. P., & Groot, de, H. W. H. (2010). A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. In Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASSCC.2010.5716582
Harpe, P.J.A. ; Zhou, C. ; Philips, K.J.P. ; Groot, de, H.W.H. / A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China. Piscataway : Institute of Electrical and Electronics Engineers, 2010. pp. 1-4
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Harpe, PJA, Zhou, C, Philips, KJP & Groot, de, HWH 2010, A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. in Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4. https://doi.org/10.1109/ASSCC.2010.5716582

A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. / Harpe, P.J.A.; Zhou, C.; Philips, K.J.P.; Groot, de, H.W.H.

Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China. Piscataway : Institute of Electrical and Electronics Engineers, 2010. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Harpe PJA, Zhou C, Philips KJP, Groot, de HWH. A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. In Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China. Piscataway: Institute of Electrical and Electronics Engineers. 2010. p. 1-4 https://doi.org/10.1109/ASSCC.2010.5716582