Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-4 |
| ISBN (Print) | 978-1-4244-8300-6 |
| DOIs | |
| Publication status | Published - 2010 |
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A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC. / Harpe, P.J.A.; Zhou, C.; Philips, K.J.P.; Groot, de, H.W.H.
Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China. Piscataway : Institute of Electrical and Electronics Engineers, 2010. p. 1-4.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC
AU - Harpe, P.J.A.
AU - Zhou, C.
AU - Philips, K.J.P.
AU - Groot, de, H.W.H.
PY - 2010
Y1 - 2010
N2 - Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a non-oversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using calibration techniques. A 2-channel time-interleaved 5 bit asynchronous digital slope ADC was implemented in a 90 nm CMOS technology. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1 V supply.
AB - Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a non-oversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using calibration techniques. A 2-channel time-interleaved 5 bit asynchronous digital slope ADC was implemented in a 90 nm CMOS technology. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1 V supply.
U2 - 10.1109/ASSCC.2010.5716582
DO - 10.1109/ASSCC.2010.5716582
M3 - Conference contribution
SN - 978-1-4244-8300-6
SP - 1
EP - 4
BT - Proceedings of the 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 8-10 November 2010, Bejing, China
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -