A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes

P.J.A. Harpe; G. Dolmans; K.J.P. Philips; H.W.H. Groot, de

doi:10.1109/ESSCIRC.2012.6341363

A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes

P.J.A. Harpe, G. Dolmans, K.J.P. Philips, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

35 Citations (Scopus)

2 Downloads (Pure)

Abstract

This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8–6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.

Original language	English
Title of host publication	Proceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	373-376
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341363
Publication status	Published - 2012
Event	38th European Solid-State Circuits Conference (ESSCIRC 2012) - Bordeaux Convention Center, Bordeaux, France Duration: 17 Sept 2012 → 21 Sept 2012 Conference number: 38

Conference

Conference	38th European Solid-State Circuits Conference (ESSCIRC 2012)
Abbreviated title	ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	17/09/12 → 21/09/12

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10.1109/ESSCIRC.2012.6341363

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Harpe, P. J. A., Dolmans, G., Philips, K. J. P., & Groot, de, H. W. H. (2012). A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes. In Proceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France (pp. 373-376). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2012.6341363

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title = "A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes",

abstract = "This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8–6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.",

author = "P.J.A. Harpe and G. Dolmans and K.J.P. Philips and {Groot, de}, H.W.H.",

year = "2012",

doi = "10.1109/ESSCIRC.2012.6341363",

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publisher = "Institute of Electrical and Electronics Engineers",

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note = "38th European Solid-State Circuits Conference (ESSCIRC 2012), ESSCIRC 2012 ; Conference date: 17-09-2012 Through 21-09-2012",

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Harpe, PJA , Dolmans, G, Philips, KJP & Groot, de, HWH 2012, A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes. in Proceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France. Institute of Electrical and Electronics Engineers, Piscataway, pp. 373-376, 38th European Solid-State Circuits Conference (ESSCIRC 2012), Bordeaux, France, 17/09/12. https://doi.org/10.1109/ESSCIRC.2012.6341363

A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes. / Harpe, P.J.A.; Dolmans, G.; Philips, K.J.P. et al.
Proceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France. Piscataway: Institute of Electrical and Electronics Engineers, 2012. p. 373-376.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8–6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.

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Harpe PJA , Dolmans G, Philips KJP, Groot, de HWH. A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes. In Proceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France. Piscataway: Institute of Electrical and Electronics Engineers. 2012. p. 373-376 doi: 10.1109/ESSCIRC.2012.6341363

A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes

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