A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes

P.J.A. Harpe, G. Dolmans, K.J.P. Philips, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

32 Citations (Scopus)
2 Downloads (Pure)


This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8–6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.
Original languageEnglish
Title of host publicationProceedings of the 42nd European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2012
Event38th European Solid-State Circuits Conference (ESSCIRC 2012) - Bordeaux Convention Center, Bordeaux, France
Duration: 17 Sept 201221 Sept 2012
Conference number: 38


Conference38th European Solid-State Circuits Conference (ESSCIRC 2012)
Abbreviated titleESSCIRC 2012


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