A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami; Kushal Dakshina Murthy; Pieter Harpe; Marian Verhelst

doi:10.1109/VLSIC.2018.8502343

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami
, Kushal Dakshina Murthy
, Pieter Harpe
, Marian Verhelst

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

Abstract

This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers
Pages	241-242
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502343
Publication status	Published - 25 Oct 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Conference

Conference	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

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10.1109/VLSIC.2018.8502343

Cite this

@inproceedings{5e6e403055254b6cb1a7143e57d1e581,

title = "A 0.6V 54DB SNR Analog Frontend with 0.18\% THD for Low Power Sensory Applications in 65NM CMOS",

abstract = "This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18\% THD at 75\% full-scale while consuming only 1.8μW power consumption.",

author = "Komail Badami and Murthy, \{Kushal Dakshina\} and Pieter Harpe and Marian Verhelst",

year = "2018",

month = oct,

day = "25",

doi = "10.1109/VLSIC.2018.8502343",

language = "English",

pages = "241--242",

booktitle = "2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

}

Badami, K, Murthy, KD, Harpe, P & Verhelst, M 2018, A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502343, Institute of Electrical and Electronics Engineers, pp. 241-242, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIC.2018.8502343

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. / Badami, Komail; Murthy, Kushal Dakshina; Harpe, Pieter et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers, 2018. p. 241-242 8502343.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

AU - Badami, Komail

AU - Murthy, Kushal Dakshina

AU - Harpe, Pieter

AU - Verhelst, Marian

PY - 2018/10/25

Y1 - 2018/10/25

N2 - This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

AB - This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

UR - https://www.scopus.com/pages/publications/85056854323

U2 - 10.1109/VLSIC.2018.8502343

DO - 10.1109/VLSIC.2018.8502343

M3 - Conference contribution

AN - SCOPUS:85056854323

SP - 241

EP - 242

BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

PB - Institute of Electrical and Electronics Engineers

T2 - 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018

Y2 - 18 June 2018 through 22 June 2018

ER -

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

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