A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami, Kushal Dakshina Murthy, Pieter Harpe, Marian Verhelst

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PublisherInstitute of Electrical and Electronics Engineers
Pages241-242
Number of pages2
ISBN (Electronic)9781538667002
DOIs
Publication statusPublished - 22 Oct 2018
Event32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
Duration: 18 Jun 201822 Jun 2018

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2018-June

Conference

Conference32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
CountryUnited States
CityHonolulu
Period18/06/1822/06/18

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