A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami; Kushal Dakshina Murthy; Pieter Harpe; Marian Verhelst

doi:10.1109/VLSIC.2018.8502343

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami, Kushal Dakshina Murthy, Pieter Harpe, Marian Verhelst

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers
Pages	241-242
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502343
Publication status	Published - 22 Oct 2018
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Conference

Conference	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Access to Document

10.1109/VLSIC.2018.8502343

Link to publication in Scopus

Cite this

Badami, K., Murthy, K. D., Harpe, P., & Verhelst, M. (2018). A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 241-242). [8502343] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSIC.2018.8502343

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abstract = "This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.",

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Badami, K, Murthy, KD, Harpe, P & Verhelst, M 2018, A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502343, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers, pp. 241-242, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIC.2018.8502343

A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. / Badami, Komail; Murthy, Kushal Dakshina; Harpe, Pieter; Verhelst, Marian.

2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers, 2018. p. 241-242 8502343 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Badami K, Murthy KD, Harpe P, Verhelst M. A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers. 2018. p. 241-242. 8502343. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2018.8502343