A 0.47–1.6 mW 5-bit 0.5–1 GS/s time-interleaved SAR ADC for low-power UWB radios

P.J.A. Harpe, B. Büsze, K.J.P. Philips, H.W.H. Groot, de

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23 Citations (Scopus)
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Abstract

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.
Original languageEnglish
Pages (from-to)1594-1602
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue number7
DOIs
Publication statusPublished - 2012

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