This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.
|Title of host publication||Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2011|
Harpe, P. J. A., Büsze, B., Philips, K. J. P., & Groot, de, H. W. H. (2011). A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios. In Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland (pp. 147-150). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2011.6044886