A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios

P.J.A. Harpe; B. Büsze; K.J.P. Philips; H.W.H. Groot, de

doi:10.1109/ESSCIRC.2011.6044886

A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios

P.J.A. Harpe, B. Büsze, K.J.P. Philips, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

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Abstract

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

Original language	English
Title of host publication	Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	147-150
ISBN (Print)	978-1-4577-0703-2
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6044886
Publication status	Published - 2011

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Harpe, P. J. A., Büsze, B., Philips, K. J. P., & Groot, de, H. W. H. (2011). A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios. In Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland (pp. 147-150). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2011.6044886

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title = "A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios",

abstract = "This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.",

author = "P.J.A. Harpe and B. B{\"u}sze and K.J.P. Philips and {Groot, de}, H.W.H.",

year = "2011",

doi = "10.1109/ESSCIRC.2011.6044886",

language = "English",

isbn = "978-1-4577-0703-2",

pages = "147--150",

booktitle = "Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Harpe, PJA, Büsze, B, Philips, KJP & Groot, de, HWH 2011, A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios. in Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland. Institute of Electrical and Electronics Engineers, Piscataway, pp. 147-150. https://doi.org/10.1109/ESSCIRC.2011.6044886

A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios. / Harpe, P.J.A.; Büsze, B.; Philips, K.J.P. et al.
Proceedings of the 37th European Solid-State Circuits Conference (ESSCIRC '11), 12-16 September 2011, Helsinki, Finland. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 147-150.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

AB - This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

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ER -

A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios

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