A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

Yuting Shen; Hanyue Li; Eugenio Cantatore; Pieter Harpe

doi:10.1109/LSSC.2020.3017874

A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

Yuting Shen (Corresponding author)
, Hanyue Li
, Eugenio Cantatore
, Pieter Harpe

Research output: Contribution to journal › Article › Academic › peer-review

128 Downloads (Pure)

Abstract

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

Original language	English
Article number	9171283
Pages (from-to)	322-325
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	3
DOIs	https://doi.org/10.1109/LSSC.2020.3017874
Publication status	Published - 2020

Funding

Manuscript received May 18, 2020; revised July 11, 2020; accepted August 14, 2020. Date of publication August 19, 2020; date of current version September 11, 2020. This article was approved by Associate Editor Qiuting Huang. This work was supported by the Dutch Research Council (NWO) under Project 16594. (Corresponding author: Yuting Shen.) The authors are with the Integrated Circuits Group, Eindhoven University of Technology, 5600 MB Eindhoven, The Netherlands (e-mail: [email protected]). Digital Object Identifier 10.1109/LSSC.2020.3017874

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Adaptable
chip-to-chip
digital communication interface
energy efficiency
full duplex

Access to Document

10.1109/LSSC.2020.3017874

publisher versionFinal published version, 1.39 MBLicence: TAVERNE

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title = "A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability",

abstract = "This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10\textasciicircum{}\{-12\}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\textbackslash{}times to 27\textbackslash{}times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\textbackslash{}times to 11\textbackslash{}times for data rates from 100 kb/s to 50 Mb/s.",

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author = "Yuting Shen and Hanyue Li and Eugenio Cantatore and Pieter Harpe",

year = "2020",

doi = "10.1109/LSSC.2020.3017874",

language = "English",

volume = "3",

pages = "322--325",

journal = "IEEE Solid-State Circuits Letters",

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A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability. / Shen, Yuting (Corresponding author); Li, Hanyue; Cantatore, Eugenio et al.
In: IEEE Solid-State Circuits Letters, Vol. 3, 9171283, 2020, p. 322-325.

Research output: Contribution to journal › Article › Academic › peer-review

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AU - Shen, Yuting

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AU - Cantatore, Eugenio

AU - Harpe, Pieter

PY - 2020

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N2 - This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

AB - This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

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KW - chip-to-chip

KW - digital communication interface

KW - energy efficiency

KW - full duplex

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A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

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UN SDGs

Keywords

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