A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

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Abstract

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

Original languageEnglish
Article number9171283
Pages (from-to)322-325
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume3
DOIs
Publication statusPublished - 2020

Keywords

  • Adaptable
  • chip-to-chip
  • digital communication interface
  • energy efficiency
  • full duplex

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