A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios

P.J.A. Harpe, X. Huang, Xiaoyan Wang, G. Dolmans, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.
Original languageEnglish
Title of host publicationProceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
ISBN (Print)978-1-4244-8500-0
DOIs
Publication statusPublished - 2011

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Radio receivers
Electric power utilization
Capacitors

Cite this

Harpe, P. J. A., Huang, X., Wang, X., Dolmans, G., & Groot, de, H. W. H. (2011). A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios. In Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VDAT.2011.5783588
Harpe, P.J.A. ; Huang, X. ; Wang, Xiaoyan ; Dolmans, G. ; Groot, de, H.W.H. / A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios. Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan. Piscataway : Institute of Electrical and Electronics Engineers, 2011. pp. 1-4
@inproceedings{80551a2f8344495ca3b5f730140c5275,
title = "A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios",
abstract = "This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.",
author = "P.J.A. Harpe and X. Huang and Xiaoyan Wang and G. Dolmans and {Groot, de}, H.W.H.",
year = "2011",
doi = "10.1109/VDAT.2011.5783588",
language = "English",
isbn = "978-1-4244-8500-0",
pages = "1--4",
booktitle = "Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Harpe, PJA, Huang, X, Wang, X, Dolmans, G & Groot, de, HWH 2011, A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios. in Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4. https://doi.org/10.1109/VDAT.2011.5783588

A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios. / Harpe, P.J.A.; Huang, X.; Wang, Xiaoyan; Dolmans, G.; Groot, de, H.W.H.

Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan. Piscataway : Institute of Electrical and Electronics Engineers, 2011. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios

AU - Harpe, P.J.A.

AU - Huang, X.

AU - Wang, Xiaoyan

AU - Dolmans, G.

AU - Groot, de, H.W.H.

PY - 2011

Y1 - 2011

N2 - This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.

AB - This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.

U2 - 10.1109/VDAT.2011.5783588

DO - 10.1109/VDAT.2011.5783588

M3 - Conference contribution

SN - 978-1-4244-8500-0

SP - 1

EP - 4

BT - Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Harpe PJA, Huang X, Wang X, Dolmans G, Groot, de HWH. A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios. In Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan. Piscataway: Institute of Electrical and Electronics Engineers. 2011. p. 1-4 https://doi.org/10.1109/VDAT.2011.5783588