A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios

P.J.A. Harpe, X. Huang, Xiaoyan Wang, G. Dolmans, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
1 Downloads (Pure)


This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.
Original languageEnglish
Title of host publicationProceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4244-8500-0
Publication statusPublished - 2011


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