A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

Georgi I. Radulov, Patrick Quinn

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.
Original languageEnglish
Title of host publicationECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)9781728171838
DOIs
Publication statusPublished - 9 Oct 2020
Event24th European Conference on Circuit Theory and Design, ECCTD 2020 - Sofia, Bulgaria
Duration: 7 Sep 202010 Sep 2020
Conference number: 24

Conference

Conference24th European Conference on Circuit Theory and Design, ECCTD 2020
Country/TerritoryBulgaria
CitySofia
Period7/09/2010/09/20

Keywords

  • DAC
  • array
  • calibration

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