A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

Georgi I. Radulov; Patrick Quinn

doi:10.1109/ECCTD49232.2020.9218326

A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

Georgi I. Radulov, Patrick Quinn

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.

Original language	English
Title of host publication	ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Electronic)	9781728171838
DOIs	https://doi.org/10.1109/ECCTD49232.2020.9218326
Publication status	Published - 9 Oct 2020
Event	24th European Conference on Circuit Theory and Design, ECCTD 2020 - Sofia, Bulgaria Duration: 7 Sept 2020 → 10 Sept 2020 Conference number: 24

Conference

Conference	24th European Conference on Circuit Theory and Design, ECCTD 2020
Country/Territory	Bulgaria
City	Sofia
Period	7/09/20 → 10/09/20

Keywords

DAC
array
calibration

Access to Document

10.1109/ECCTD49232.2020.9218326

Cite this

@inproceedings{bf57a5a0001c4a2c943db3877b6c45c2,

title = "A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz",

abstract = "This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.",

keywords = "DAC, array, calibration",

author = "Radulov, {Georgi I.} and Patrick Quinn",

year = "2020",

month = oct,

day = "9",

doi = "10.1109/ECCTD49232.2020.9218326",

language = "English",

booktitle = "ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "24th European Conference on Circuit Theory and Design, ECCTD 2020 ; Conference date: 07-09-2020 Through 10-09-2020",

}

Radulov, GI & Quinn, P 2020, A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz. in ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design., 9218326, Institute of Electrical and Electronics Engineers, 24th European Conference on Circuit Theory and Design, ECCTD 2020, Sofia, Bulgaria, 7/09/20. https://doi.org/10.1109/ECCTD49232.2020.9218326

A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz. / Radulov, Georgi I.; Quinn, Patrick.
ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design. Institute of Electrical and Electronics Engineers, 2020. 9218326.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

AU - Radulov, Georgi I.

AU - Quinn, Patrick

N1 - Conference code: 24

PY - 2020/10/9

Y1 - 2020/10/9

N2 - This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.

AB - This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.

KW - DAC

KW - array

KW - calibration

UR - http://www.scopus.com/inward/record.url?scp=85096482515&partnerID=8YFLogxK

U2 - 10.1109/ECCTD49232.2020.9218326

DO - 10.1109/ECCTD49232.2020.9218326

M3 - Conference contribution

BT - ECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design

PB - Institute of Electrical and Electronics Engineers

T2 - 24th European Conference on Circuit Theory and Design, ECCTD 2020

Y2 - 7 September 2020 through 10 September 2020

ER -

A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this