A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

Pieter J.A. Harpe

doi:10.1109/CICC.2019.8780319

A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter

Pieter J.A. Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

7 Downloads (Pure)

Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Original language	English
Title of host publication	2019 IEEE Custom Integrated Circuits Conference, CICC 2019
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Electronic)	978-1-5386-9395-7
DOIs	https://doi.org/10.1109/CICC.2019.8780319
Publication status	Published - 1 Apr 2019
Event	2019 IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States Duration: 14 Apr 2019 → 17 Apr 2019 Conference number: 40

Conference

Conference	2019 IEEE Custom Integrated Circuits Conference, CICC 2019
Country/Territory	United States
City	Austin
Period	14/04/19 → 17/04/19

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10.1109/CICC.2019.8780319

Cite this

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title = "A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter",

abstract = "This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.",

author = "Harpe, {Pieter J.A.}",

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doi = "10.1109/CICC.2019.8780319",

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note = "2019 IEEE Custom Integrated Circuits Conference, CICC 2019 ; Conference date: 14-04-2019 Through 17-04-2019",

}

Harpe, PJA 2019, A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter. in 2019 IEEE Custom Integrated Circuits Conference, CICC 2019., 8780319, Institute of Electrical and Electronics Engineers, Piscataway, 2019 IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, Texas, United States, 14/04/19. https://doi.org/10.1109/CICC.2019.8780319

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N2 - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

AB - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

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M3 - Conference contribution

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PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2019 IEEE Custom Integrated Circuits Conference, CICC 2019

Y2 - 14 April 2019 through 17 April 2019

ER -

A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter

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