A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

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Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Original languageEnglish
Title of host publication2019 IEEE Custom Integrated Circuits Conference, CICC 2019
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)978-1-5386-9395-7
DOIs
Publication statusPublished - 1 Apr 2019
Event40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
Duration: 14 Apr 201917 Apr 2019

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
CountryUnited States
CityAustin
Period14/04/1917/04/19

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Cite this

Harpe, P. J. A. (2019). A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. In 2019 IEEE Custom Integrated Circuits Conference, CICC 2019 [8780319] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/CICC.2019.8780319