A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

Pieter Harpe

doi:10.1109/CICC.2018.8357059

A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter

Pieter Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

11 Citations (Scopus)

6 Downloads (Pure)

Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Original language	English
Title of host publication	2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Electronic)	978-1-5386-2483-8
ISBN (Print)	978-1-5386-2484-5
DOIs	https://doi.org/10.1109/CICC.2018.8357059
Publication status	Published - 9 May 2018
Event	2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States Duration: 8 Apr 2018 → 11 Apr 2018

Conference

Conference	2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Abbreviated title	CICC 2018
Country/Territory	United States
City	San Diego
Period	8/04/18 → 11/04/18

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10.1109/CICC.2018.8357059

Cite this

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title = "A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter",

abstract = "This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.",

author = "Pieter Harpe",

year = "2018",

month = may,

day = "9",

doi = "10.1109/CICC.2018.8357059",

language = "English",

isbn = "978-1-5386-2484-5",

booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018, CICC 2018 ; Conference date: 08-04-2018 Through 11-04-2018",

}

Harpe, P 2018, A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018., 8357059, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, California, United States, 8/04/18. https://doi.org/10.1109/CICC.2018.8357059

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N2 - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

AB - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

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BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Y2 - 8 April 2018 through 11 April 2018

ER -

A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter

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