A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

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Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Original languageEnglish
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)978-1-5386-2483-8
ISBN (Print)978-1-5386-2484-5
DOIs
Publication statusPublished - 9 May 2018
Event2018 IEEE Custom Integrated Circuits Conference (CICC 2018) - San Diego, United States
Duration: 8 Apr 201811 Apr 2018

Conference

Conference2018 IEEE Custom Integrated Circuits Conference (CICC 2018)
Abbreviated titleCICC 2018
CountryUnited States
CitySan Diego
Period8/04/1811/04/18

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Harpe, P. (2018). A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 [8357059] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/CICC.2018.8357059