A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

LanguageEnglish
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
Number of pages4
ISBN (Electronic)978-1-5386-2483-8
ISBN (Print)978-1-5386-2484-5
DOIs
StatePublished - 9 May 2018
Event2018 IEEE Custom Integrated Circuits Conference (CICC 2018) - San Diego, United States
Duration: 8 Apr 201811 Apr 2018

Conference

Conference2018 IEEE Custom Integrated Circuits Conference (CICC 2018)
Abbreviated titleCICC 2018
CountryUnited States
CitySan Diego
Period8/04/1811/04/18

Fingerprint

Anti-aliasing
Passive filters
FIR filters
Capacitors

Cite this

Harpe, P. (2018). A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/CICC.2018.8357059
Harpe, Pieter. / A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Piscataway : Institute of Electrical and Electronics Engineers, 2018. pp. 1-4
@inproceedings{cb8c66f89e6d4f0c992f805372739c84,
title = "A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter",
abstract = "This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.",
author = "Pieter Harpe",
year = "2018",
month = "5",
day = "9",
doi = "10.1109/CICC.2018.8357059",
language = "English",
isbn = "978-1-5386-2484-5",
pages = "1--4",
booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Harpe, P 2018, A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4, 2018 IEEE Custom Integrated Circuits Conference (CICC 2018), San Diego, United States, 8/04/18. DOI: 10.1109/CICC.2018.8357059

A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. / Harpe, Pieter.

2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Piscataway : Institute of Electrical and Electronics Engineers, 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

AU - Harpe,Pieter

PY - 2018/5/9

Y1 - 2018/5/9

N2 - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

AB - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

UR - http://www.scopus.com/inward/record.url?scp=85048090585&partnerID=8YFLogxK

U2 - 10.1109/CICC.2018.8357059

DO - 10.1109/CICC.2018.8357059

M3 - Conference contribution

SN - 978-1-5386-2484-5

SP - 1

EP - 4

BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Harpe P. A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Piscataway: Institute of Electrical and Electronics Engineers. 2018. p. 1-4. Available from, DOI: 10.1109/CICC.2018.8357059