Abstract
This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.
| Original language | English |
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| Title of host publication | ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference |
| Publisher | IEEE Computer Society |
| Pages | 531-534 |
| Number of pages | 4 |
| ISBN (Print) | 9781457707018 |
| DOIs | |
| Publication status | Published - 12 Dec 2011 |
| Externally published | Yes |
| Event | 37th European Solid-State Circuits Conference (ESSCIRC 2011) - Finlandia Hall, Helsink, Finland Duration: 12 Sept 2011 → 16 Sept 2011 Conference number: 37 http://www.esscirc2011.org |
Conference
| Conference | 37th European Solid-State Circuits Conference (ESSCIRC 2011) |
|---|---|
| Abbreviated title | ESSCIRC 2011 |
| Country/Territory | Finland |
| City | Helsink |
| Period | 12/09/11 → 16/09/11 |
| Internet address |