8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes

Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)

Abstract

This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

Original languageEnglish
Title of host publicationESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
PublisherIEEE Computer Society
Pages531-534
Number of pages4
ISBN (Print)9781457707018
DOIs
Publication statusPublished - 12 Dec 2011
Externally publishedYes
Event37th European Solid-State Circuits Conference (ESSCIRC 2011) - Finlandia Hall, Helsink, Finland
Duration: 12 Sep 201116 Sep 2011
Conference number: 37
http://www.esscirc2011.org

Conference

Conference37th European Solid-State Circuits Conference (ESSCIRC 2011)
Abbreviated titleESSCIRC 2011
CountryFinland
CityHelsink
Period12/09/1116/09/11
Internet address

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