8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes

Vibhu Sharma; Stefan Cosemans; Maryam Ashouei; Jos Huisken; Francky Catthoor; Wim Dehaene

doi:10.1109/ESSCIRC.2011.6044939

8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes

Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

Abstract

This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Publisher	IEEE Computer Society
Pages	531-534
Number of pages	4
ISBN (Print)	9781457707018
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6044939
Publication status	Published - 12 Dec 2011
Externally published	Yes
Event	37th European Solid-State Circuits Conference (ESSCIRC 2011) - Finlandia Hall, Helsink, Finland Duration: 12 Sept 2011 → 16 Sept 2011 Conference number: 37 http://www.esscirc2011.org

Conference

Conference	37th European Solid-State Circuits Conference (ESSCIRC 2011)
Abbreviated title	ESSCIRC 2011
Country/Territory	Finland
City	Helsink
Period	12/09/11 → 16/09/11
Internet address	http://www.esscirc2011.org

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ESSCIRC.2011.6044939

Cite this

Sharma, V., Cosemans, S., Ashouei, M., Huisken, J., Catthoor, F., & Dehaene, W. (2011). 8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference (pp. 531-534). Article 6044939 IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2011.6044939

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title = "8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes",

abstract = "This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.",

author = "Vibhu Sharma and Stefan Cosemans and Maryam Ashouei and Jos Huisken and Francky Catthoor and Wim Dehaene",

year = "2011",

month = dec,

day = "12",

doi = "10.1109/ESSCIRC.2011.6044939",

language = "English",

isbn = "9781457707018",

pages = "531--534",

booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

address = "United States",

note = "37th European Solid-State Circuits Conference (ESSCIRC 2011), ESSCIRC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

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}

Sharma, V, Cosemans, S, Ashouei, M, Huisken, J, Catthoor, F & Dehaene, W 2011, 8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6044939, IEEE Computer Society, pp. 531-534, 37th European Solid-State Circuits Conference (ESSCIRC 2011), Helsink, Finland, 12/09/11. https://doi.org/10.1109/ESSCIRC.2011.6044939

8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes. / Sharma, Vibhu; Cosemans, Stefan; Ashouei, Maryam et al.
ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. IEEE Computer Society, 2011. p. 531-534 6044939.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Sharma, Vibhu

AU - Cosemans, Stefan

AU - Ashouei, Maryam

AU - Huisken, Jos

AU - Catthoor, Francky

AU - Dehaene, Wim

N1 - Conference code: 37

PY - 2011/12/12

Y1 - 2011/12/12

N2 - This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

AB - This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

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U2 - 10.1109/ESSCIRC.2011.6044939

DO - 10.1109/ESSCIRC.2011.6044939

M3 - Conference contribution

AN - SCOPUS:82955194807

SN - 9781457707018

SP - 531

EP - 534

BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference

PB - IEEE Computer Society

T2 - 37th European Solid-State Circuits Conference (ESSCIRC 2011)

Y2 - 12 September 2011 through 16 September 2011

ER -

8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes

Abstract

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UN SDGs

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