3D test: no longer a bottleneck!

Erik Jan Marinissen (Corresponding author)

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When I joined imec in October 2008 to work on test and design-for-test (DfT) of 3D-stacked integrated circuits (ICs), there were only a few test folks active in that emerging field. Consequently, misconceptions about 3D test were omni-present. In the November 18, 2008 issue of Semiconductor International, Alexander Braun wrote: “At a symposium yesterday on 3-D integration, leading expert Philip Garrou detailed the rise of the technology as well as the challenges facing it, including test, yield, and design. (…) Test, again, will be a significant problem. Memory can be stacked as known good die, because the memory chips can be tested, but years from now, as different functions are pulled apart to stack them, there is no clear way to test them because they do not form a complete circuit. This will hold up things like the full partitioning of chips.”1 3D InCites’ tenth anniversary is a good occasion to report on the state of 3D testing and publicly declare that it's no longer a bottleneck for 3D integration.
Original languageEnglish
Pages (from-to)21-26 + 60
Number of pages7
Journal3DInCites: The First Decade
Issue number1
Publication statusPublished - 8 Mar 2019


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