3D passive and heterogeneous integration technology options for system-in-package

F. Roozeboom, J.H. Klootwijk, W. Dekkers, K.B. Jinesh, Y. Lamy, E.C.E. Grunsven, van, M. Burghoorn, F. Sanders, M.A. Verheijen, R.G.R. Weemaes, M. Kaiser, T. Sakai, H.-D. Kim, D. Blin, S.B.S. Heil, M.C.M. Sanden, van de, W.M.M. Kessels

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic


Future generations of cellular RF transceivers require higher degrees of integration, presumably using the third dimension. This paper describes technologies that we recently studied and which have found or may soon find their implementation in RF and other System-in-Package (SiP) applications. In passive integration we describe options to integrate 3D 'trench' capacitors in silicon with a new world record capacitance density of = 400 nF/mm1 and break-down voltage> 6 V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (AI20 3) and conductive layers (TiN). We also describe a few through-silicon via (TSV) drilling and filling techniques for 3D die and wafer stacking and generic SiP integration with a small rorm factor. Here, dry and wet-chemical methods were applied successfully in both the drilling and filling. We compare RIE etching and (photo)chemical etching, the latter method yielding ultrafine high aspect ratio (-1.5 x200 Ilm) vias. We report on a 'bottom-up' Cu-electroplating method and on some preliminary eu-paste tilling tests.
Original languageEnglish
Title of host publicationProceedings 2nd IEEE Workshop on 3D System Integration, Munich, Germany
Place of PublicationMünchen, Germany
Publication statusPublished - 2007
Eventconference; International Workshop 3D System Integration; 2007-10-01; 2007-10-02 -
Duration: 1 Oct 20072 Oct 2007


Conferenceconference; International Workshop 3D System Integration; 2007-10-01; 2007-10-02
OtherInternational Workshop 3D System Integration


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