3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer

Engineering

• Integrated Circuit 100%
• Silicon 100%
• Interposer 100%
• Electronics 100%
• Optical Interconnection 25%
• Performance 16%
• Modules 16%
• Receivers 16%
• Bit Error Rate 16%
• Testing 8%
• Fabrication 8%
• Cavity 8%
• Process Flow 8%
• Chip Bonding 8%

Physics

• Silicon 100%
• Performance 16%
• Air 16%
• Gaps 16%
• Isolation 16%
• Probe 16%
• Bit Error Rate 16%
• Fabrication 8%
• Station 8%
• Optics 8%
• Etching 8%
• Multiple Mirror Telescope 8%
• Chipping 8%

Material Science

• Heat Transfer 25%
• Air 16%
• Wet Etching 8%