Abstract
| Original language | English |
|---|---|
| Title of host publication | 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 551-556 |
| ISBN (Electronic) | 978-1-5090-6315-4 |
| ISBN (Print) | 978-1-5090-6316-1 |
| DOIs | |
| Publication status | Published - 2017 |
Fingerprint
Cite this
}
3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. / Li, C.; Smalbrugge, E.; Li, T.; Stabile, R.; Raz, O.
67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida. Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 551-556.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - 3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer
AU - Li, C.
AU - Smalbrugge, E.
AU - Li, T.
AU - Stabile, R.
AU - Raz, O.
PY - 2017
Y1 - 2017
N2 - In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 μm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver
AB - In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 μm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver
U2 - 10.1109/ECTC.2017.222
DO - 10.1109/ECTC.2017.222
M3 - Conference contribution
SN - 978-1-5090-6316-1
SP - 551
EP - 556
BT - 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -