3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer

C. Li, E. Smalbrugge, T. Li, R. Stabile, O. Raz

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 μm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver
Original languageEnglish
Title of host publication67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages551-556
ISBN (Electronic)978-1-5090-6315-4
ISBN (Print)978-1-5090-6316-1
DOIs
Publication statusPublished - 2017

Fingerprint

Packaging
Silicon
Bit error rate
Optical interconnects
Wet etching
Air
Optics
Electronic equipment
Heat transfer
Fabrication
Testing
Hot Temperature

Cite this

Li, C., Smalbrugge, E., Li, T., Stabile, R., & Raz, O. (2017). 3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. In 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida (pp. 551-556). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ECTC.2017.222
Li, C. ; Smalbrugge, E. ; Li, T. ; Stabile, R. ; Raz, O. / 3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida. Piscataway : Institute of Electrical and Electronics Engineers, 2017. pp. 551-556
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abstract = "In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 μm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver",
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Li, C, Smalbrugge, E, Li, T, Stabile, R & Raz, O 2017, 3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. in 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida. Institute of Electrical and Electronics Engineers, Piscataway, pp. 551-556. https://doi.org/10.1109/ECTC.2017.222

3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. / Li, C.; Smalbrugge, E.; Li, T.; Stabile, R.; Raz, O.

67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida. Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 551-556.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 μm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver

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Li C, Smalbrugge E, Li T, Stabile R, Raz O. 3D packaging of embeded opto-electronic die and CMOS IC based on wet etched silicon interposer. In 67th Electronic Components and Technology Conference (ECTC), 30 May - 2 June 2017, Orlando, Florida. Piscataway: Institute of Electrical and Electronics Engineers. 2017. p. 551-556 https://doi.org/10.1109/ECTC.2017.222