IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.
|Title of host publication||Handbook of 3D integration|
|Subtitle of host publication||volume 4: design, test, and thermal management|
|Editors||P.D. Franzon, E.J. Marinissen, M.S. Bakir|
|Place of Publication||Weinheim|
|Number of pages||28|
|Publication status||Published - 8 Feb 2019|