3D design‐for‐test architecture

Erik Jan Marinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi, Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin, Brion L. Keller, Vivek Chickermane, Sandeep K. Goel

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Abstract

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.
Original languageEnglish
Title of host publicationHandbook of 3D integration
Subtitle of host publicationvolume 4: design, test, and thermal management
EditorsP.D. Franzon, E.J. Marinissen, M.S. Bakir
Place of PublicationWeinheim
PublisherWiley-VCH Verlag
Chapter12
Pages253-280
Number of pages28
ISBN (Print)978-3-527-33855-9
DOIs
Publication statusPublished - 8 Feb 2019

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    Marinissen, E. J., Konijnenburg, M., Verbree, J., Chi, C-C., Deutsch, S., Papameletis, C., ... Goel, S. K. (2019). 3D design‐for‐test architecture. In P. D. Franzon, E. J. Marinissen, & M. S. Bakir (Eds.), Handbook of 3D integration: volume 4: design, test, and thermal management (pp. 253-280). Weinheim: Wiley-VCH Verlag. https://doi.org/10.1002/9783527697052.ch12