3D design‐for‐test architecture

Erik Jan Marinissen; Mario Konijnenburg; Jouke Verbree; Chun-Chuan Chi; Sergej Deutsch; Christos Papameletis; Tobias Burgherr; Konstantin Shibin; Brion L. Keller; Vivek Chickermane; Sandeep K. Goel

doi:10.1002/9783527697052.ch12

3D design‐for‐test architecture

Erik Jan Marinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi, Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin, Brion L. Keller, Vivek Chickermane, Sandeep K. Goel

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

Abstract

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.

Original language	English
Title of host publication	Handbook of 3D integration
Subtitle of host publication	volume 4: design, test, and thermal management
Editors	P.D. Franzon, E.J. Marinissen, M.S. Bakir
Place of Publication	Weinheim
Publisher	Wiley-VCH Verlag
Chapter	12
Pages	253-280
Number of pages	28
ISBN (Print)	978-3-527-33855-9
DOIs	https://doi.org/10.1002/9783527697052.ch12
Publication status	Published - 8 Feb 2019

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Marinissen, E. J., Konijnenburg, M., Verbree, J., Chi, C-C., Deutsch, S., Papameletis, C., ... Goel, S. K. (2019). 3D design‐for‐test architecture. In P. D. Franzon, E. J. Marinissen, & M. S. Bakir (Eds.), Handbook of 3D integration: volume 4: design, test, and thermal management (pp. 253-280). Weinheim: Wiley-VCH Verlag. https://doi.org/10.1002/9783527697052.ch12

Marinissen, Erik Jan ; Konijnenburg, Mario ; Verbree, Jouke ; Chi, Chun-Chuan ; Deutsch, Sergej ; Papameletis, Christos ; Burgherr, Tobias ; Shibin, Konstantin ; Keller, Brion L. ; Chickermane, Vivek ; Goel, Sandeep K. / 3D design‐for‐test architecture. Handbook of 3D integration: volume 4: design, test, and thermal management. editor / P.D. Franzon ; E.J. Marinissen ; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. pp. 253-280

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abstract = "IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.",

author = "Marinissen, {Erik Jan} and Mario Konijnenburg and Jouke Verbree and Chun-Chuan Chi and Sergej Deutsch and Christos Papameletis and Tobias Burgherr and Konstantin Shibin and Keller, {Brion L.} and Vivek Chickermane and Goel, {Sandeep K.}",

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Marinissen, EJ, Konijnenburg, M, Verbree, J, Chi, C-C, Deutsch, S, Papameletis, C, Burgherr, T, Shibin, K, Keller, BL, Chickermane, V & Goel, SK 2019, 3D design‐for‐test architecture. in PD Franzon, EJ Marinissen & MS Bakir (eds), Handbook of 3D integration: volume 4: design, test, and thermal management. Wiley-VCH Verlag, Weinheim, pp. 253-280. https://doi.org/10.1002/9783527697052.ch12

3D design‐for‐test architecture. / Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion L.; Chickermane, Vivek; Goel, Sandeep K.

Handbook of 3D integration: volume 4: design, test, and thermal management. ed. / P.D. Franzon; E.J. Marinissen; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. p. 253-280.

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

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