Abstract
| Language | English |
|---|---|
| Title of host publication | Handbook of 3D integration |
| Subtitle of host publication | volume 4: design, test, and thermal management |
| Editors | P.D. Franzon, E.J. Marinissen, M.S. Bakir |
| Place of Publication | Weinheim |
| Publisher | Wiley-VCH Verlag |
| Chapter | 12 |
| Pages | 253-280 |
| Number of pages | 28 |
| ISBN (Print) | 978-3-527-33855-9 |
| DOIs | |
| State | Published - 8 Feb 2019 |
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3D design‐for‐test architecture. / Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion L.; Chickermane, Vivek; Goel, Sandeep K.
Handbook of 3D integration: volume 4: design, test, and thermal management. ed. / P.D. Franzon; E.J. Marinissen; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. p. 253-280.Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review
TY - CHAP
T1 - 3D design‐for‐test architecture
AU - Marinissen,Erik Jan
AU - Konijnenburg,Mario
AU - Verbree,Jouke
AU - Chi,Chun-Chuan
AU - Deutsch,Sergej
AU - Papameletis,Christos
AU - Burgherr,Tobias
AU - Shibin,Konstantin
AU - Keller,Brion L.
AU - Chickermane,Vivek
AU - Goel,Sandeep K.
PY - 2019/2/8
Y1 - 2019/2/8
N2 - IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.
AB - IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.
U2 - 10.1002/9783527697052.ch12
DO - 10.1002/9783527697052.ch12
M3 - Chapter
SN - 978-3-527-33855-9
SP - 253
EP - 280
BT - Handbook of 3D integration
PB - Wiley-VCH Verlag
CY - Weinheim
ER -