30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents a 30-GHz co-design of a 28-dB high-gain low-noise amplifier (LNA) and a 54% high-efficiency monopole antenna-on-chip for 5G wireless applications. The LNA design is based on a two-stage differential cascode structure with inductive degeneration. The antenna design is a modified monopole structure to maximize the radiation efficiency. Both parts are integrated directly on the same silicon chip in a 0.25 µm SiGe BiCMOS technology. A co-design method is proposed according to various considerations and a compact matching network is implemented to achieve the optimal power and noise matching. The measurement results show a total gain of 27 dB of the complete system.
Original languageEnglish
Title of host publication2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages3
ISBN (Electronic)978-1-7281-2496-4
DOIs
Publication statusPublished - Aug 2019
Event2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) - Nanjing, China
Duration: 28 Aug 201930 Aug 2019

Conference

Conference2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
CountryChina
CityNanjing
Period28/08/1930/08/19

Fingerprint

Low noise amplifiers
Antennas
BiCMOS technology
Monopole antennas
Radiation
Silicon

Cite this

Chen, Z., Liu, Q., Smolders, B., Baltus, P., & Gao, H. (2019). 30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications. In 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) [8929159] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIT.2019.8929159
Chen, Zhe ; Liu, Qiang ; Smolders, Bart ; Baltus, Peter ; Gao, Hao. / 30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications. 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway : Institute of Electrical and Electronics Engineers, 2019.
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abstract = "This paper presents a 30-GHz co-design of a 28-dB high-gain low-noise amplifier (LNA) and a 54{\%} high-efficiency monopole antenna-on-chip for 5G wireless applications. The LNA design is based on a two-stage differential cascode structure with inductive degeneration. The antenna design is a modified monopole structure to maximize the radiation efficiency. Both parts are integrated directly on the same silicon chip in a 0.25 µm SiGe BiCMOS technology. A co-design method is proposed according to various considerations and a compact matching network is implemented to achieve the optimal power and noise matching. The measurement results show a total gain of 27 dB of the complete system.",
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Chen, Z, Liu, Q, Smolders, B, Baltus, P & Gao, H 2019, 30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications. in 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)., 8929159, Institute of Electrical and Electronics Engineers, Piscataway, 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nanjing, China, 28/08/19. https://doi.org/10.1109/RFIT.2019.8929159

30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications. / Chen, Zhe; Liu, Qiang; Smolders, Bart; Baltus, Peter; Gao, Hao.

2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway : Institute of Electrical and Electronics Engineers, 2019. 8929159.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - This paper presents a 30-GHz co-design of a 28-dB high-gain low-noise amplifier (LNA) and a 54% high-efficiency monopole antenna-on-chip for 5G wireless applications. The LNA design is based on a two-stage differential cascode structure with inductive degeneration. The antenna design is a modified monopole structure to maximize the radiation efficiency. Both parts are integrated directly on the same silicon chip in a 0.25 µm SiGe BiCMOS technology. A co-design method is proposed according to various considerations and a compact matching network is implemented to achieve the optimal power and noise matching. The measurement results show a total gain of 27 dB of the complete system.

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Chen Z, Liu Q, Smolders B, Baltus P, Gao H. 30-GHz co-designed low-noise amplifier and antenna-on-chip for wireless applications. In 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway: Institute of Electrical and Electronics Engineers. 2019. 8929159 https://doi.org/10.1109/RFIT.2019.8929159