3-Dimensional passive and heterogeneous integration technology options for system-in-package

F. Roozeboom, J.H. Klootwijk, W. Dekkers, K.B. Jinesh, Y. Lamy, E.C.E. Grunsven, van, M. Burghoorn, F.H.M. Sanders, M.A. Verheijen, R.G.R. Weemaes, M. Kaiser, T. Sakai, H.-D. Kim, D. Blin, S.B.S. Heil, M.C.M. Sanden, van de, W.M.M. Kessels

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Abstract

Future generations of cellular RF transceivers require higher degrees of integration, presumably using the third dimension. This paper describes technologies that we recently studied and which have found or may soon find their implementation in RF and other System-in-Package (SiP) applications. In passive integration we describe options to integrate 3D ‘trench’ capacitors in silicon with a new world record capacitance density of ³ 400 nF/mm2 and break-down voltage > 6 V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (Al2O3) and conductive layers (TiN). We also describe a few through-silicon via (TSV) drilling and filling techniques for 3D die and wafer stacking and generic SiP integration with a small form factor.Here, dry and wet-chemical methods were applied successfully in both the drilling and filling.We compare RIE etching and (photo)chemical etching, the latter method yielding ultrafine high aspect ratio (~1.5×200 µm) vias.We report on a ‘bottom-up’ Cuelectroplating method and on some preliminary Cu-paste filling tests.
Original languageEnglish
Title of host publicationSmart system integration and reliability : a special edition on the occasion of Herbert Reichl’s 65th birthday
EditorsB. Michel, K.D. Lang
Place of PublicationDresden
PublisherGoldenbogen Verlag
Pages120-131
Number of pages12
Publication statusPublished - 2010

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