Abstract
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS technology for ultra wide band (UWB) receivers. The flash ADC is suitable for the high speed and low resolution application because of its fast speed and simple structure. In the ultra high speed situation, the track and hold amplifier and the comparator is the bottle neck for the whole ADC. In this paper the sense amplifier based comparator and the symmetric S-R latch can improve the performance of comparator thus will improve the performance of the whole ADC. Compared with the traditional comparator, the proposed comparator runs faster and provides more stable output even at the 2GHz sampling frequency. The proposed Flash ADC achieves 5.4-bit effective number of bits (ENOB) for input signal of 100MHz at 2GSample/sec. And the power consumption is 124.03mW with 1.2V supply voltage.
| Original language | English |
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| Title of host publication | 2010 International Symposium on Signals, Systems and Electronics (ISSSE), 17-20 September 2010, Nanjing, China |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 130-134 |
| Number of pages | 5 |
| Volume | 1 |
| ISBN (Print) | 978-1-4244-6352-7 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China - Nanjing, China Duration: 17 Sept 2010 → 20 Sept 2010 |
Conference
| Conference | 2010 International Symposium on Signals, Systems and Electronics (ISSSE 2010), September 17-20, 2010, Nanjing, China |
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| Country/Territory | China |
| City | Nanjing |
| Period | 17/09/10 → 20/09/10 |