160-Gb/s Optical packet switching subsystem with a monolithic optical phased-array switch

I.M. Soganci; N. Calabretta; T. Tanemura; W. Wang; O. Raz; K. Higuchi; K.A. Williams; T. Vries, de; H.J.S. Dorren; Y. Nakano

doi:10.1109/LPT.2010.2046161

160-Gb/s Optical packet switching subsystem with a monolithic optical phased-array switch

I.M. Soganci, N. Calabretta, T. Tanemura, W. Wang, O. Raz, K. Higuchi, K.A. Williams, T. Vries, de, H.J.S. Dorren, Y. Nakano

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Abstract

1 × 8 and 1 × 16 optical packet switching (OPS) node subsystems are demonstrated. The OPS node consists of a 1 × N monolithically integrated InP optical phased-array switch, an electronic switch controller, and a label extractor/eraser that utilizes cascaded reflective fiber Bragg gratings. In-band parallel labels are employed to encode the address information. 160-Gb/s optical time-domain-multiplexed packets are dynamically switched to 8 and 16 outputs with power penalties of 0.5 and 0.7 dB, respectively.

Original language	English
Pages (from-to)	817-819
Number of pages	3
Journal	IEEE Photonics Technology Letters
Volume	22
Issue number	11
DOIs	https://doi.org/10.1109/LPT.2010.2046161
Publication status	Published - 2010

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title = "160-Gb/s Optical packet switching subsystem with a monolithic optical phased-array switch",

abstract = "1 × 8 and 1 × 16 optical packet switching (OPS) node subsystems are demonstrated. The OPS node consists of a 1 × N monolithically integrated InP optical phased-array switch, an electronic switch controller, and a label extractor/eraser that utilizes cascaded reflective fiber Bragg gratings. In-band parallel labels are employed to encode the address information. 160-Gb/s optical time-domain-multiplexed packets are dynamically switched to 8 and 16 outputs with power penalties of 0.5 and 0.7 dB, respectively.",

author = "I.M. Soganci and N. Calabretta and T. Tanemura and W. Wang and O. Raz and K. Higuchi and K.A. Williams and \{Vries, de\}, T. and H.J.S. Dorren and Y. Nakano",

year = "2010",

doi = "10.1109/LPT.2010.2046161",

language = "English",

volume = "22",

pages = "817--819",

journal = "IEEE Photonics Technology Letters",

issn = "1041-1135",

publisher = "Institute of Electrical and Electronics Engineers",

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TY - JOUR

T1 - 160-Gb/s Optical packet switching subsystem with a monolithic optical phased-array switch

AU - Soganci, I.M.

AU - Calabretta, N.

AU - Tanemura, T.

AU - Wang, W.

AU - Raz, O.

AU - Higuchi, K.

AU - Williams, K.A.

AU - Vries, de, T.

AU - Dorren, H.J.S.

AU - Nakano, Y.

PY - 2010

Y1 - 2010

N2 - 1 × 8 and 1 × 16 optical packet switching (OPS) node subsystems are demonstrated. The OPS node consists of a 1 × N monolithically integrated InP optical phased-array switch, an electronic switch controller, and a label extractor/eraser that utilizes cascaded reflective fiber Bragg gratings. In-band parallel labels are employed to encode the address information. 160-Gb/s optical time-domain-multiplexed packets are dynamically switched to 8 and 16 outputs with power penalties of 0.5 and 0.7 dB, respectively.

AB - 1 × 8 and 1 × 16 optical packet switching (OPS) node subsystems are demonstrated. The OPS node consists of a 1 × N monolithically integrated InP optical phased-array switch, an electronic switch controller, and a label extractor/eraser that utilizes cascaded reflective fiber Bragg gratings. In-band parallel labels are employed to encode the address information. 160-Gb/s optical time-domain-multiplexed packets are dynamically switched to 8 and 16 outputs with power penalties of 0.5 and 0.7 dB, respectively.

U2 - 10.1109/LPT.2010.2046161

DO - 10.1109/LPT.2010.2046161

M3 - Article

SN - 1041-1135

VL - 22

SP - 817

EP - 819

JO - IEEE Photonics Technology Letters

JF - IEEE Photonics Technology Letters

IS - 11

ER -

160-Gb/s Optical packet switching subsystem with a monolithic optical phased-array switch

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