1000-Pixels Per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan (Corresponding author), Joris de Riet, Thijs Bel, Ilias Katsouras, Lucasz Witczak, Auke Jisk Kronemeijer, René A.J. Janssen, Gerwin H. Gelinck

Research output: Contribution to journalLetterAcademicpeer-review


Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7 μm, field-effect mobility of 10 cm2 V-1 s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.
Original languageEnglish
Pages (from-to)1217-1220
JournalIEEE Electron Device Letters
Issue number8
Publication statusPublished - 1 Aug 2020

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