1000-Pixels Per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan; Joris de Riet; Thijs Bel; Ilias Katsouras; Lucasz Witczak; Auke Jisk Kronemeijer; René A.J. Janssen; Gerwin H. Gelinck

doi:10.1109/LED.2020.3006343

1000-Pixels Per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Tamer Dogan (Corresponding author), Joris de Riet, Thijs Bel, Ilias Katsouras, Lucasz Witczak, Auke Jisk Kronemeijer, René A.J. Janssen, Gerwin H. Gelinck

Research output: Contribution to journal › Article › Academic › peer-review

4 Citations (Scopus)

Abstract

Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7 μm, field-effect mobility of 10 cm2 V-1 s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.

Original language	English
Article number	9130793
Pages (from-to)	1217-1220
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	41
Issue number	8
DOIs	https://doi.org/10.1109/LED.2020.3006343
Publication status	Published - 1 Aug 2020

Funding

Manuscript received May 29, 2020; revised June 25, 2020; accepted June 28, 2020. Date of publication July 1, 2020; date of current version July 24, 2020. This work was supported in part by the European Regional Development Fund through the Flexlines Project through the Interreg V-Program Flanders-The Netherlands, a Cross-Border Cooperation Program, in part by the Province of Noord-Brabant, The Netherlands, and in part by the King Abdullah University of Science and Technology (KAUST) Office for Sponsored Research (OSR) under Award OSR-CRG2018-3783. The review of this letter was arranged by Editor S. Zhang. (Corresponding author: Tamer Dogan.) Tamer Dogan and Gerwin H. Gelinck are with the TNO/Holst Centre, 5656 Eindhoven, The Netherlands, and also with the Department of Applied Physics, Eindhoven University of Technology, 5600 Eindhoven, The Netherlands (e-mail: [email protected]).

Keywords

High-resolution thin film transistor array
amorphous Indium Gallium Zinc Oxide thin film transistor
multi-level nanoimprint lithography

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10.1109/LED.2020.3006343

Cite this

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abstract = "Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7 μm, field-effect mobility of 10 cm2 V-1 s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.",

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1000-Pixels Per Inch Transistor Arrays Using Multi-Level Imprint Lithography

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