1-D discrete time CNN with multiplexed template hardware

G. Manganaro, J. Pineda de Gyvez

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    Abstract

    While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S2I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architecture
    Original languageEnglish
    Title of host publicationProceedings of the Fifth IEEE International Workshop on Cellular Neural Networks and their Applications, 14-17 April 1998, London, United Kingdom
    Place of PublicationNew York
    PublisherInstitute of Electrical and Electronics Engineers
    Pages265-270
    ISBN (Print)0-7803-4867-2
    DOIs
    Publication statusPublished - 1998

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