Roel Jordans is an Assistant Professor in the Electronic Systems group of the Electrical Engineering Department at Eindhoven University of Technology (TU/e). His research interests include developing hardware architectures for reliable, high-performance systems and compilation techniques for and design automation applied to application-specific processors.  

Jordans supports processor architecture research teams with developing the compilers for their architectures. He provides workshops and direct support, both for industrial partners as for TU/e's own coarse-grain reconfigurable architecture (CGRA) and single instruction, multiple data (SIMD) architectures.  

Jordans worked on the STARS-JITC RP project, focusing on just-in-time compilation for reconfigurable platforms. He is currently also active in the NCLE  and Auger Radio Upgrade projects at the Radboud RadioLab, which is part of their Astrophysics department. In Ireland, Jordans was part of a research collaboration through a HiPEAC Collaboration grant, where he investigated the possibilities of high-level software pipelining in LLVM. 

For his PhD research, Jordans worked on automatic very long instruction word (VLIW) data-path synthesis for ASIPs, trying to find the optimal issue width and instruction set of a VLIW processor based on the target application. He also explored a VLIW-based processor architecture based on these estimates, combining the strengths of the LLVM compiler framework with custom exploration strategies.